The present invention relates to the field of hardware emulation and testing.
A critical step in the characterization and bringup test of integrated circuits is the test of the array elements or memories they contain. An array element or memory array, in the sense of the present text is, e.g., an L2 cache. It comprises memory cells (the array memory) as well as associated read and write logic to access these cells.
Complex test programs are executed on wafer test systems (testers) in order to check the quality of the arrays. One important function of these test programs is to determine the exact location of failing single-bit memory cells. The process is called Bit Fail Mapping, because maps of bit fails are constructed that provide insight into the weaknesses of the circuit and valuable feedback for circuit design and technology.
Traditionally, developing these test programs for the wafer test systems is extremely difficult because there is no reliable test object against which the test programs could be checked for correctness. Old circuits cannot be used easily as the test programs are highly customized for a specific chip. Furthermore, the actual chip does not provide reliable single bit fails, as it is the device under test (DUT). Also, when the actual chip is available, the test program must already be error-free, and its development should already be complete.
Running the developed test programs against a DUT simulation is not practically possible. Running the test program on a simulation system requires multiple transformation steps. These too are likely to introduce new errors, thereby rendering such a solution not practical.
Emulation lends itself as a solution to this problem. Logic circuits can be emulated by directly attaching an emulation system to the wafer tester. Hence, logic emulation without error injection is commonly used. Also, error injection is possible, since non-array signals can be controlled during the runtime of the emulation system. Without error injection, the array circuits can be emulated. In contrast, emulation with error injection is practically impossible for arrays. The reason is that the arrays of the design are mapped to internal memories of the emulation machine. As such, they are not controllable by software running on the emulation machine. Single array cells cannot be simply stuck by software on the emulation machine. Bit Fail Mapping, however, requires single array cells to be stuck reliably and without impact on emulation performance.
As a remedy one could model arrays as single latches on the emulation machine. But the required amount of emulation resource for this approach is prohibitive. In practice, the test programs are first developed without testing, and checked using actual chips after they arrived from the wafer fabrication. To provide reliable injected errors on actual chips, single bit cells are physically destroyed using the FIB (Focused Ion Beam) method. Such a treatment of wafers is expensive and very time-consuming, since it is done by external companies. It is also error-prone, because the different logical and physical layout of a memory needs to be taken into account.
U.S. Pat. No. 6,829,572 discloses a method and system in a logic simulator machine for overriding a value of a net in an array during execution of a test routine while the logic simulator machine is simulating a logic design. Although this principally enables sticking of single array cells in a simulation system, sticks have to be renewed per simulation cycle.
White paper ‘Accelerated Hardware/Software Co-Verification’ of Cadence Design Systems, Inc. discloses a logic simulator for modeling an ASIC (Application Specific Integrated Circuit) and all other hardware components in a logic design except the processor and memory. The memory is ‘modeled’ by workstation memory, which as a result prevents injection of control and stuck of errors, and thus limits the possibility of emulating erroneous arrays.